【2013学术报告2】VLSI Design Optimization for Signal Processing Systems
Title: VLSI Design Optimization for Signal Processing Systems
Speaker: Dr. Zhongfeng Wang
Time: 10:30AM，May 23, 2013
Place: 1-312, FIT Building
Organizer: Research Institute of Information Technology (RIIT), Tsinghua University
Dr. Zhongfeng Wang entered Tsinghua University in 1983 without normal high school education. He received both Bachelor and Master degrees from Dept. of Automation. He obtained the Ph.D. degree from the Department of Electrical and Computer Engineering at the University of Minnesota, Minneapolis. He is now an Associate Technical Director at Broadcom Corporation, California. Before that, he was an Assistant Professor at Oregon State University. Even earlier he was working for National Semiconductor Incorporation. He also holds a Professor Adjunct position at a few universities including the University of Colorado and Nanjing University.
Dr. Wang is a world-recognized expert on Low-Power High-Speed VLSI Design for Signal Processing Systems. He has published over one hundred technical papers with two best paper awards received in the IEEE Circuits and Systems (CAS) society. He has edited one book “VLSI” and filed over thirty U.S. patent applications and disclosures. In the current record (2007-2009), he is the only author in the research society with three papers ranking among top ten most downloaded manuscripts in IEEE Trans. on VLSI Systems. In the past ten years, he has served as Associate Editor for IEEE Trans. on CAS-I, CAS-II, and VLSI Systems for numerous terms. He has been serving in three technical committees in the IEEE CAS society and Signal Processing society. In 2013, he served in the annual best paper award selection committee in the IEEE CAS society. Moreover, he has contributed significantly to the industrial standards. Particularly, he is the key contributor in defining Forward Error Correction (FEC) schemes and Data Synchronization schemes for IEEE 100Gbps Ethernet over Backplane and Copper Cable standards (IEEE P802.3bj). His current research interests are in the area of Low Power/High Speed VLSI Design for High-Speed Networking Systems.
As VLSI technology continues to scale down, more and more complex signal processing algorithms such as Low-Density Parity-Check (LDPC) coding, MIMO detection, and Maximum Likelihood Sequence Estimation (MLSE) are integrated into a single chip to improve the system performance, which usually lead to large power consumption and hardware cost. On the other hand, the desire for high data-rate communications such as 100Gb Ethernet, low packaging cost, and long battery life for wireless or portable devices has continued to increase. Thus VLSI design optimization for modern digital communication systems has become more and more critical.
In this talk, following a brief overview of CMOS IC design basics, three major optimization goals, i.e., low power, high speed and low latency, will be addressed. Generic techniques as well as commonly used application-specific design methods for each optimization target will be briefly discussed. Instead of explaining these fundamental techniques in detail, the talk will be focused on illustration of some state-of-the-art designs for each design objective.